The present invention relates to an image processor for selectively processing for output a two-dimensional image projected onto an image sensor or compressing the two-dimensional image.
Description is made hereinafter for an image processor based on the conventional technology. It should be noted that the description of ordinary processing for outputting a two-dimensional image projected onto an image sensor is omitted herein. As literature related to the image processor based on the conventional technology which can output projection data for a two-dimensional image, for example, there is Japanese Patent Laid-Open Publication No. HEI 10-093358.
FIG. 10 shows a configuration of an image processor based on the conventional technology. In FIG. 10, designated at the reference numeral 101 is a plurality of unit pixel circuits connected to each other in an array each for outputting a pixel value for one pixel to output lines 103 and 104, at 102 a vertical scanning circuit for scanning the unit pixel circuits 101 in the vertical direction, at 105 a plurality of offset read circuits provided in each column for inverting either one of the output lines 103 and 104 and connected to the output terminal 106 through a transmission gate, and at 107 a horizontal scanning circuit for scanning the plurality of offset read circuits 105 in the horizontal direction.
FIG. 11 shows a circuit configuration of the unit pixel circuit 101. In FIG. 11, designated at the reference numeral 113 is an optoelectronic transducer for accumulating electric charge of the pixel generated due to the incident light and changing an output potential according to the amount of light, at 112 a MOS transistor for resetting the optoelectronic transducer to a source potential 111, at 115 and 116 are transistors for negative and positive output respectively for outputting a current flowing through the MOS transistor 114.
Description is made hereinafter for the operation so as to obtain projection data for a two-dimensional image in the conventional type of image processor configured as described above. At first, each optoelectronic transducer 113 of each of the unit pixel circuits 101 is reset to a source potential 111 (by controlling a signal Vr in the figure). In this state, conductance of the MOS transistor 114 is changed as the electric charge is accumulated in the optoelectronic transducer 113 due to the incident light.
The MOS transistor 114 amplifies output of the optoelectronic transducer 113, and further a current flowing through the MOS transistor 114 is outputted to an output terminal 117 (corresponding to a signal Vout1 in the figure) or 118 (corresponding to a signal Vout2 in the figure) under the control of the transistor 115 for negative output or the transistor 116 for positive output (by controlling a signal Vn or a signal Vp in the figure is controlled) by the vertical scanning circuit 102.
Then, when each signal Vn or signal Vp in all the rows is scanned by the vertical scanning circuit 102, each data corresponding to a total sum of currents from all the unit pixel circuits in each column, namely a total sum of pixel values according to the amount of incident light is obtained in each offset read circuit 105. Then, a one-dimensional projection, namely a projection of a light pattern irradiated onto the two-dimensional unit pixel circuit can be obtained through scanning by the horizontal scanning circuit 107. As another literature related to the image processor based on the conventional technology which can output projection data for a two-dimensional image, for example, there is Japanese Patent Laid-Open Publication No. HEI 5-111010. It should be noted that the description of ordinary processing for outputting a two-dimensional image projected onto an image sensor is omitted herein.
FIG. 12 shows a configuration of an image processor based on the conventional technology. In FIG. 12, each of the reference numerals 12011, 12012, . . . , 120mn (m and n: arbitrary integers) indicates a structure of a unit pixel referred to as a charge modulation device (CMD), the CMDs are arranged in a matrix, a video voltage VDD is commonly applied to each drain thereof, row lines 1221, 1222, . . . , 122m, are connected to gates, and column lines 1241, 1242, . . . , 124n are connected to sources respectively.
The column lines 1241, 1242, . . . , 124n are connected to a video line (output line for outputting image signal) 130 as well as to a line 132 with a voltage V (xe2x89xa70) applied thereto through transistors 1261, 1262, . . . , 126n for column selection (first MOS switches) as well as through transistors 1281, 1282, . . . , 128n for inverse selection respectively. The video line 130 is grounded through load resistance 134, and reads a signal through an output terminal 136. It should be noted that a variable source-voltage pulse train Vs is loaded onto the output terminal 136 by an illustrated external on-chip circuit or some other external circuit.
Further, the row lines 1221, 1222, . . . , 122m are connected to the vertical scanning circuit 138, and vertical scan signals xcfx86G1, xcfx86G2, . . . , xcfx86Gm are applied thereonto respectively, while the gates of the column-selection transistors 1261, 1262, . . . , 126n as well as of the inverse selection transistors 1281, 1282, . . . , 128n are connected to the horizontal scanning circuit 140, and horizontal scan signals xcfx86S1, xcfx86S2, . . . , xcfx86Sn as well as the inverse signals thereof are applied to the gates respectively. It is assumed that the CMDs are formed on the same substrate and a substrate voltage Vsub (not shown) is applied to the substrate.
In the conventional type of image processor configured as described above, for example, by concurrently setting the signals xcfx86G1, xcfx86G2, . . . , xcfx86Gm to an ON state with the vertical scanning circuit 138, all the pixels from the first row to the m-th row each connected to column are selected, and a sum of signal currents is read out. Then, a one-dimensional projection of a light pattern irradiated onto each of the two-dimensional CMDs can be obtained through scanning (by controlling the signals xcfx86S1, xcfx86S2, . . . , xcfx86Sn) by the horizontal scanning circuit 140.
As described above, in the conventional type of image processor, the ordinary processing for outputting a two-dimensional image projected onto an image sensor is executable and also the processing for outputting projection data for the two-dimensional image is executable.
However, in the conventional type of image processor, computing is performed by adding (summing) currents of all the pixels constituting each line, and so, the output level when a gradation signal (pixel value) is read out from one pixel is largely different from that when a result of the computing for projection is read out, namely an electric current value for the result of the computing for projection becomes extremely large.
As described above, the fact that an electric current in computing for projection becomes extremely large and so requires a large amount of power.
In addition, in order to suppress the difference between the output level when a gradation signal (pixel value) is read out from a pixel and that when a result of the computing for projection is read out, types of power units (such as a low-potential power unit) are required to be increased.
In addition, output is easily a nonlinear xe2x80x98amount of lightxe2x80x99xc3x97xe2x80x98number of pixelsxe2x80x99 due to saturation of the added currents, there-fore, in order to maintain the linearity, number of pixels capable of being added disadvantageously becomes extremely small.
It is an object of the present invention to obtain, for the purpose of solving the problems as described above, an image processor in which an output level and a level of power consumption are equalized to each other between ordinary processing for outputting a two-dimensional image projected onto an image sensor and processing for outputting a result of the computing for the two-dimensional image.
With the present invention, a result of computing for projection is an average of pixel values in the unit pixel circuits constituting each row and column, so that, as is in the conventional type, an output level when a gradation signal (pixel value) is read out from a pixel is not largely different from that when a result of computing for projection is read out, and an electric current value in the result of computing for projection does not become extremely large. As a result, power consumption can largely be reduced as compared to that of the conventional type.
With the present invention, for example, when a result of computing for projection in a row direction forming an array is read out, electric charge is accumulated in an optoelectronic transducer due to the incident light, and an output potential generated due to the electric charge is changed. The potential amplified by a buffer circuit is stored in a memory for a unit pixel circuit according to the output potential. Then, all the corresponding pixel values are read out to an output line under the control of a switching circuit corresponding to the row direction. It should be noted that, in the processing for reading out a result of computing for projection, namely in the processing of compressing a two-dimensional image, i.e., the computing for projection, this pixel-value read-out processing is performed in all the unit pixel circuits at the same time, and at this point of time, the charge is re-distributed on the output line, so that a result of the computing for projection as an average of pixel values in unit pixel circuits can be obtained.
With this operation, it is not required to suppress the difference between the output level when a gradation signal (pixel value) is read out from each unit pixel circuit and that when a result of the computing for projection is read out, there fore, the types of power units (such as a low-potential power unit) need not be increased. In addition, access is made to all the unit pixel circuits at the same time to average the potentials, which allows the linearity of xe2x80x98amount of lightxe2x80x99xc3x97xe2x80x98number of pixelsxe2x80x99 to be improved.
With the present invention, an offset of an optoelectronic transducer and a memory for a unit pixel circuit is accurately carried out, so that reliability of pixel values is enhanced.
With the present invention, by controlling an image-data read circuit, a pixel value of each unit pixel circuit stored in the memory capacitor for a read circuit and a result of computing for projection of each row and each column can be read out any time until new data is stored therein. Both of the output levels are equivalent to each other, so that the types of power units are not required to be increased.
With the present invention, an offset of a memory for a read circuit is accurately carried out, and further the memory capacitor for a read circuit can be insulated from an output line, so that reliability of image data to be read out is enhanced.
With the present invention, a difference between a specified reference value and image data for a current frame can be obtained, so that the offset in output of pixels can be removed by using two memory capacities for a read circuit, and as a result, variations among pixels can be suppressed. In addition, a difference between image data for a previous frame and that for a current frame can be obtained, so that a result of computing for projection can also be subjected to time differentiation.
In accordance with the present invention, an average of pixel values (image data) in all the unit pixel circuits can be outputted through the same processing as computing for projection. Therefore, the amount of computations required, for example, when an optimal output gain is adjusted from the average value of an amount of light incident upon an image-pickup surface and when an accumulation time is optimized is largely reduced by a circuit provided in the later stage, namely by DSP or the like.
In accordance with the present invention, a difference between a specified reference value and a result of computing the average value of all the pixels in a current frame can be obtained, so that the offset in a result of computing the average value of all the pixels can be removed by using two memory capacities for a read circuit. In addition, a difference between a result of computing the average value of all the pixels in a previous frame and that in a current frame can be obtained, so that a result of computing the average value can also be subjected to time differentiation.
In accordance with the present invention, it is possible to output, for example, by assigning a weight of 2 to certain image data and a weight of xe2x88x921 to the adjacent two pixels, a difference therebetween. Therefore, an equivalent result to one-dimensional filtering processing can be obtained, so that the data in a state where filtering is performed can be outputted.
In accordance with the present invention, in the processing of computing for projection, signal charge (potential) is re-distributed on an output line, so that even a case of 100xc3x97100 pixels, substantially only a time spent for 100xc3x972 pixels is required (because computation for projection for 100xc3x97100 rows can be performed at a time, and then computation for projection for 100xc3x97100 columns can be performed at a time), therefore, a read-out time required for the processing of computing for projection can be speeded up.
In accordance with the present invention, in the processing of reading out a pixel value for each pixel, buffered pixel values are read out directly to an output line without execution of processing for storing the value in the memory capacitor for a unit pixel circuit, so that a time required for the processing of reading out a two-dimensional image can be speeded up.
In accordance with the present invention, the obtained result of computing for projection is an average of the signal charges stored in the memory capacitor constituting each row and each column, so that, as is in the conventional type, an output level when a gradation signal (pixel value) is read out from a pixel is not largely different from that when a result of computing for projection is read out, and a current value in the result of computing for projection does not become extremely large. As a result, power consumption can largely be reduced as compared to that of the conventional type.